As information processing circuits progress towards higher levels of integration, there is growth in array size for cache and imbedded arrays, there is increased use of cache in high data volume machines, and with increased used of CMOS arrays in large, so called high end data processing machines, there are pressures to decrease the size of CMOS SRAM cells. Without such decrease in size it is necessary to make investments in larger chips, more aggressive lithography, and vertical enhancements. Such investments greatly increase the cost of the chips.
In addition to the requirement for reduced area, electrical requirements for SRAM cells are becoming more stringent. For example, increased reliability standards have resulted in larger device ratios being required in current products.
Soft error rate (SER) is also of great concern. Projections from prior work and preliminary sizing of cells used on 4 megabyte chips indicate that enhancement of stored charge will in all probability be required to avoid excessive SER. Without added capacitance the indigeneous static stored charge may be inadequate to prevent upset in the stored data due to "funneled" charge (field enhanced collection) that is collected too rapidly for the current from the p-devices to compensate.
Another problem associated with smaller cells, is the need for more complex and therefore thinner wiring of reduced pitch at the so called back end of the line (BEOL) levels needed to make interconnections to logic and SRAM peripheral circuitry. It is desirable to have a layout and process for dense SRAM cells which allows presently available BEOL wiring to be used, thus avoiding the cost and reliability problems associated with reduced pitch size wiring.